实现一个CPU模拟器，可以执行ARM指令集。
Assignment Overview
The overall aim of your assignment is to build a software based implementation of a
Central Processing Unit (CPU). Such an implementation should be capable of emulating the execution of machine code instructions. The implementation should be written in the ‘C’ programming language but you are free to use ‘C++’ if you are more comfortable with the latter. You are free to use any compiler you wish, however the GNU tool-chain is recommended. CPUs can clearly be very complex devices, hence you will not be expected to build a fully compliant implementation. However the more complete the implementation, the higher the final grade will be. The CPU to be simulated will be loosely based on the standard ARM architecture. You will be provided with a datasheet which will specify the nature of the device (e.g, register count, status register format etc. and the instruction set to be supported). In order for the simulation to work your program will also have to provide some virtual peripheral devices, e.g. Some virtual RAM will be required and virtual display?.
The project has been broken down into three requirements described as follows.
Requirement 1 - Instruction Decoding and Disassembling
The first requirement will be to develop a program which is capable of decoding ARM based instructions from their native form (machine code) and displaying these as Assembly language instructions. This should result in the development of a computer program which has the ability to fetch, decode and display the instructions within the provided instruction set.
One key aspect you will have to consider is how the instructions will be defined and read by your program. The op-codes should be stored in your virtual RAM (or ROM if you decide to include such a feature). However these codes need to get into the virtual machine somehow. Initially you may want to consider hard-coding some simple instructions for testing purposes. Later you may decide to load the instructions from a file.
As the program is executing it should display the original op-code value along with the assembly language equivalent. For example, given the following machine code hexadecimal op-codes -
E3 A0 00 01
E3 A0 10 02
E0 80 20 01
E2 82 20 05
The program should output something similar to the following.
Op-Code Assembly Mnemonic
-----------------------------------
E3 A0 00 01 MOV r0,#l
E3 A0 10 02 MOV rl,#2
E0 80 20 01 ADD r2,r0,rl
E2 82 20 05 ADD r2,r2,#5
Requirement 2 - Basic Emulation
The second requirement of the assignment is to extend the implementation so that as well as displaying each Assembly language instruction it should also emulate the behaviour of these, i.e. implement a basic CPU emulator. For this requirement only the basic ALU type instructions need to be supported, e.g. ADD, SUB, CMP, MOV. Also conditional execution of each instruction does NOT yet need to be supported.
In order to achieve this you will need to create variables to represent the internal “state” of the CPU. For example, you will need to be able to store the current contents of each of the 16 registers. It is recommended that all registers are initially set to 0 (except R13 which should be set to the top of stack position).
As the program is executing it should display the same output as requirement 1, plus the contents of each of the sixteen registers. This way the correct execution of each instruction will be verifiable. It may be a good idea to pause between each instruction and wait until the user presses the enter key before proceeding. For example -
Op-Code Assembly Mnemonic
-----------------------------------
E3 A0 00 01 MOV rQf#l
R0: 00000001 R1: 00000000 r2: 00000000 r3: 00000000
R4: 00000000 R5: 00000000 r6: 00000000 r7: 00000000
R8: 00000000 R9: 00000000 r10:00000000 r11:00000000
R12:00000000 R13:00010000 r14:00000000 r15:00000104
Press <return> for next instruction.
Op-Code Assembly Mnemonic
-----------------------------------
E3 A0 10 02 MOV rl,#2
R0: 00000001 R1: 00000002 r2: 00000000 r3: 00000000
R4: 00000000 R5: 00000000 r6: 00000000 r7: 00000000
R8: 00000000 R9: 00000000 r10:00000000 r11:00000000
R12:00000000 R13:00010000 r14:00000000 r15:00000108
Press <return> for next instruction.
Op-Code Assembly Mnemonic
-----------------------------------
EG 80 20 01 ADD r2,r0,r1
R0: 00000001 R1: 00000002 r2: 00000003 r3: 00000000
R4: 00000000 R5: 00000000 r6: 00000000 r7: 00000000
R8: 00000000 R9: 00000000 r10:00000000 r11:00000000
R12:00000000 R13:00010000 r14:00000000 r15:0000010C
Press <return> for next instruction.
Op-Code Assembly Mnemonic
-----------------------------------
E2 82 20 05 ADD r2,r2,#5
R0: 00000001 R1: 00000002 r2: 00000008 r3: 00000000
R4: 00000000 R5: 00000000 r6: 00000000 r7: 00000000
R8: 00000000 R9: 00000000 r10:00000000 r11:00000000
R12:00000000 R13:00010000 r14:00000000 r15:00000110
Press <return> for next instruction.
Program end. Terminating.
Requirement 3 - Full Emulation
The final requirement will be to extend requirement two so that it emulates all of the provided instruction set. So therefore the (Dranching instructions (B and BL) will need supporting as will the memory access instructions (LDR and STR), along with all instructions defined within the datasheet.
All instructions should also be extended to support conditional execution (based on condition codes). Therefore you should take care to ensure that the instructions not only undertake their operation correctly, but they also carry out appropriate side effects, such as the setting of status register flags.
To get to the highest bracket of the available marks you should also include the ability to count elapsed time during the simulation (in terms of instruction cycle usage). To implement this feature you will need to use the instruction timing information provided in the datasheet and keep a running total of total time elapsed.
MARKING SCHEME / CRITERIA
The following criteria will be taken into account during the demonstration and grading of your assignment solution. An inability to explain the code can result in a fail even if requirements are completed.